ASIC / FPGA Design Verification Engineer �

Required Qualifications

• This position requires the ability to obtain a US Security Clearance for which the US Government requires US Citizenship as a condition of employment. An interim and/or final U.S. Secret Clearance Post-Start is required.
• Bachelor of Science degree in Engineering (with a focus in Electrical, Mechanical or Aeronautical), Computer Science, Data Science, Mathematics, Physics, Chemistry or non-US equivalent qualifications directly related to the work statement
• Bachelor’s degree with 9+ years of professional engineering experience in ASIC, FPGA, or SoC design verification, OR a BS/MS and 7+ years of FPGA, ASIC, or SoC verification experience
• Strong experience with SystemVerilog for simulation testbench development and RTL debugging
• Fluent UVM experience including environment development
• 2+ projects standing up verification environments and reusable infrastructure
• Senior, Level 5: 14+ years of related engineering experience
• Bachelor’s Degree or Masters Degree in EE, Computer Engineering/Science, or related field
• Active U.S. Secret Security Clearance
• 10+ years of verification experience
• Strong understanding of Digital design fundamentals and systems awareness fundamentals
• Feature, block, subsystem, or broader verification ownership
• Metrics?driven closure experience
• Requirements traceability and measurable verification objectives
• Mentoring and indirect technical leadership experience
• Project management or technical coordination experience