Static Timing Analysis Engineer

Required Qualifications

• This position requires the ability to obtain a U.S. Security Clearance for which the U.S. Government requires U.S. Citizenship. An interim and/or final U.S. Secret, Top Secret, or Top-Secret SCI Clearance Post-Start is required.
• Bachelor of Science degree in Engineering (with a focus in Electrical, Mechanical or Aeronautical), Computer Science, Data Science, Mathematics, Physics, Chemistry or non-US equivalent qualifications directly related to the work statement
• 5+ years of experience with timing closure on ASICs and FPGAs
• Experience with several ASICs/FPGAs signoff and at least one ASIC tape-out. Good understanding of RTL to GDS flow
• Proficiency using Synopsys Primetime (or Cadence Tempus) for timing analysis and Synopsys Design Compiler (or Cadence Genus) for synthesis
• Ability to work with large physical design team to make the timing convergence successful
• Lead, Level 5: 15+ years of related work experience or an equivalent combination of education and experience
• 10 or more years of experience with timing closure on ASICs and FPGAs
• Completed multiple first-pass success ASIC tape-outs with intricacies (Cross clock domain, async crossing etc.)
• Experience in using multiple static timing tools (Cadence Tempus, Vivado, Synopsys Primetime)
• Fair knowledge of Synopsys Fusion Compiler, Formality (Cadence LEC), and other relevant tools (e.g. TCM, Fishtail)
• Synopsys physical design AI tool experience is a plus
• Experience leading static timing closure and training new hires
• Familiarity with space-based design techniques and radiation mitigation
• Understanding of design for testability (DFT) and its implications on timing
• Capable of working independently, self starter
• Proficiency with multiple scripting languages (Python, C SHELL, TCL)
• Capable of handling timing closure on multiple designs simultaneously